1. Field of the Invention
The present invention generally relates to a semiconductor device including a bit check function and a testing method using the same, and more particularly, to an improvement of a semiconductor memory device which can test a memory cell using the bit check function and a testing method using the same.
2. Description of the Background Art
In a semiconductor memory device including a bit check function (comparison function), plural-bit data stored in a memory cell and plural-bit data externally applied are verified to determine whether or not these data match each other. Upon this determination, it is determined whether or not the plural-bit data stored in the memory cell is desired data. As a result, it is determined whether the memory cell is defective or not.
A tag memory in a cash memory is taken as an example of a semiconductor memory device including a comparison function. In the tag memory, tag data in an input address is prestored. The tag data and tag data stored in a cash memory are compared during data retrieval, whereby it is determined whether these data match or not. The tag memory is used for determination of a cash hit, hit miss or the like of data in the cash memory.
FIG. 8 is a block diagram showing a configuration of a semiconductor memory device including a comparison function disclosed in Japanese Patent Laying-Open No. 4-368695. Referring to FIG. 8, the semiconductor memory device includes a plurality of word lines WL disposed in the rows, a row decoder 1 selecting one of the word lines WL, a plurality of bit line pairs BL, BL disposed in the columns crossing the word lines WL, a plurality of memory cells 4 disposed at crossing points of the word lines WL and the bit line pairs BL, BL, and a plurality of sense amplifiers 5 provided corresponding to the bit line pairs BL, BL.
Both bit lines BL and BL of each bit line pair BL, BL are respectively connected to power supply nodes 3 supplied with the power supply potential Vcc through load transistors 2. Each memory cell 4 stores one-bit data.
Therefore, when row decoder 1 selects one word line WL, data is read out from memory cells 4 connected to the word line WL to the bit line pairs BL, BL. Data signals corresponding to the data are respectively applied to sense amplifiers 5 through the bit line pairs BL, BL. In response to a corresponding data signal, each sense amplifier 5 determines whether data in the corresponding memory cell 4 is "1" or "0".
The semiconductor memory device further includes a plurality of exclusive OR gates 6 provided corresponding to sense amplifiers 5, a plurality of discharge N channel MOS transistors 7 provided corresponding to gates 6, a match line 8 connecting the drain electrodes of transistors 7 in common, and a load P channel MOS transistor 9 connected between match line 8 and a power supply node 10 supplied with the power supply potential Vcc.
The semiconductor memory device is externally supplied with n-bit reference signals RF1 to RFn. The reference signal RF1 and a data signal D from corresponding sense amplifier 5 are applied to corresponding exclusive OR gate 6. Exclusive OR gate 6 generates a result signal X in response to signals RF1 and D. Each discharge transistor 7 conducts match line 8 to a ground node in response to the result signal X from corresponding exclusive OR gate 6.
Since the gate electrode of load transistor 9 is supplied with the ground potential, transistor 9 is maintained conductive. Therefore, match line 8 is supplied with the power supply potential Vcc through transistor 9, whereby match line 8 is slightly set to an H (logic high) level. The potential of match line 8 is provided outside as a determination signal Y.
In FIG. 8, one bit line pair BL, BL, memory cells 4 connected to the one bit line pair BL, BL, load transistors 2 connected to the one bit line pair BL, BL, a sense amplifier 5 connected to the bit line pair BL, BL, and an exclusive OR gate 6 corresponding to sense amplifier 5 configure one block B1. In the semiconductor memory device, n such blocks B1 to Bn are disposed in the row direction.
It should be noted that a writing circuit to a memory cell and a column decoder for selecting a bit line pair which are not directly relevant to the present invention are not shown in FIG. 8.
Comparison operation of the semiconductor memory device of the above configuration will be described.
One word line WL is selected by row decoder 1. Data is respectively read out from n memory cells 4 connected to the selected word line WL to n bit line pairs BL, BL. Data signals corresponding to data read out from memory cells 4 appear on one bit line BL, and data signals complementary to the data signals appear on the other bit line BL.
These data signals are applied to sense amplifier 5. Sense amplifier 5 amplifies the data signals to provide one data signal D to exclusive OR gate 6. Exclusive OR gate 6 receives the data signal D provided from sense amplifier 5 and a predetermined reference signal RF1 applied externally, to generate a result signal X at an L (logic low) level if these signals match each other, and to generate a result signal X at an H level if these signals do not match each other.
Therefore, in all of the block B1 to Bn, when data signals D provided from sense amplifier 5 and externally applied reference signals RF1 to RFn respectively match each other, all the result signals X provided from the blocks B1 to Bn attain an L level. All the discharge transistors 7 are rendered non-conductive, and match line 8 is maintained at an H level. Therefore, a determination signal Y at an H level is provided, whereby it is determined that data signals D read out from memory cells 4 and externally applied reference signals RF1 to RFn all match each other.
On the other hand, when data signals D provided from sense amplifiers 5 and externally applied reference signals RF1 to RFn do not match each other even in any one block, the result signal X at an H level is provided from the block. Discharge transistor 7 which receives the result signal at an H level at its gate electrode is rendered conductive, and charge of match line 8 precharged to an H level is removed through discharge transistor 7. Therefore, the determination signal Y at an L level is provided from match line 8, whereby it is determined that at least one of n-bit data signals read out from the memory cells does not match its corresponding reference signal.
A method of testing the memory cell using the semiconductor memory device shown in FIG. 8 will be described with reference to FIG. 9. FIG. 9 is a flow chart showing a testing method for identifying a defective memory cell in four memory cells 4.
In a defective memory cell, data at an L level is read out although data at an H level is written, or data at an H level is read out although data at an L level is written. Irrespectively of a level of written data, data at an H level is always read out, or data at an L level is always read out.
According to this testing method, after four-bit data is written in four memory cells 4 to be tested, data is read out from memory cells 4. Then, the read out four-bit data and externally applied four-bit reference data are compared as described above, and it is determined whether the data match each other.
Such a comparison as described above is carried out in various combinations of written data and reference data, resulting in identification of a location of a defective memory cell.
More specifically, at step S20, data of "HHHH" is written in four memory cells 4. At step S21, data is read out from four memory cells 4.
At step S22, the read data is compared with a reference signal of "HHHH". At step S23, the read data is compared with a reference signal of "LHHH". At step S24, the read data is compared with a reference signal of "HLHH". At step S25, the read data is compared with a reference signal of "HHLH". At step S26, the read data is compared with a reference signal of "HHHL".
At step S27, after data of "LLLL" is written in four memory cells 4, data is read out from memory cells 4 at step S28. At step S29, the read data is compared with a reference signal of "LLLL". At step S30, the read data is compared with a reference signal of "HLLL". At step S30, the read data is compared with a reference signal of "LHLL". At step S32, the read data is compared with a reference signal of "LLHL". At step S33, the read data is compared with a reference signal of "LLLH".
As described above, as a result of ten comparisons of data read out from the memory cells and externally applied reference data, a defective memory cell 4 is located. When data at an L level is read out although data at an H level is written in a memory cell of the 0-th bit, for example, out of four memory cells 4 because the memory cell is defective, it is determined that a memory cell at the 0-th bit is defective since the signals match each other as a result of comparison at step S23.
On the other hand, when the signals match each other as a result of comparison at step S22, and the signals match each other as a result of comparison at step S29, it is determined that there is no defective memory cell.
According to the above testing method, when there is only one defective memory cell, the defective memory cell can be located. However, when there are a plurality of defective memory cells, it is very difficult to locate the defective memory cells.
When a data signal at an H level is always read out from a memory cell of the first bit and a data signal at an L level is always read out from a memory cell of the third bit, for example, it is necessary to write data of "HHHH" to memory cells and to sequentially compare data signals read out from the memory cells with 2.sup.4 combinations of reference signals, and further to write data of "LLLL" to the memory cells and to sequentially compare data signals read out from the memory cells again with 2.sup.4 combinations of reference signals. Therefore, (2.sup.4 .times.2) comparisons must be carried out during one test. Since the number of times of comparisons increases exponentially as increase of the number of memory cells to be tested, it is extremely difficult to locate defective memory cells in a plurality of memory cells.
As described above, in the conventional semiconductor memory device, it is possible to determine whether a defective memory cell exists or not in a plurality of memory cells 4 connected to one word line WL selected by row decoder 1. However, it is extremely difficult to locate a defective memory cell. Since an intricate test must be carried out for locating a defective memory cell, a time required for the test becomes long.